The present invention relates to lamp ballast circuits, and, more particularly, to an improved lamp ballast circuit which protects against lamp failure.
Lamp ballast circuits, such as an International Rectifier IR2155 or IR2151 IC, are known and are described in U.S. Pat. Nos. 5,545,955 and 5,559,394 to Peter Wood and in U.S. Pat. No. 5,550,436 to Talbott M. Houk.
To properly shut down a ballast IC during certain lamp application failure modes, a means of turning off the gate driver outputs upon sensing fault conditions (such as a broken filament or a lamp which fails to strike at startup) and then turning off the output power transistors is needed.
Because of the topology of the IR2155 and IR2151 ICs, the circuits are self-oscillating under normal operation, as shown in FIGS. 1 and 2.
FIG. 1 shows the components of a typical lamp driver circuit. A bridge rectifier 10 derives a bus voltage (V.sub.BUS) from the ac line. The bus voltage is approximately dc and is supported by capacitors 56 and 58.
The lamp driver circuit of FIG. 1 includes an MOS gate driver chip 30 and its associated circuitry for controlling the operation of a high side MOSFET 40 and a low side MOSFET 41. The MOS gate driver chip 30 provides drive signals to the MOSFETs 40 and 42 which are connected to V.sub.BUS. Though power MOSFETs are shown, any power device which has a MOS gate, such as an IGBT or a MOS gated thyristor, may be substituted for power MOSFETs 40 and 42.
The output of the center tap of half bridge connected MOSFETs 40 and 42 drives a circuit that includes a series LC load circuit comprised of inductor 46 and capacitor 52.
The voltage supplied at terminal V.sub.BUS can range from as low as 140 volts d-c to above 600 volts d-c, depending upon the supplied AC input voltage.
The oscillating frequency of the output circuit is controlled by the resonant frequency of the inductor 46 and the capacitor 52. The desired inductance value of inductor 46 will depend on the value of the voltage V.sub.BUS and is selected so that the oscillation frequency of the circuit is within desired range.
The chip 30 may be housed in a 8-pin DIP or surface mount package and has the following pinouts:
V.sub.CC --a pin which receives a chip operating voltage from the d-c supply V.sub.BUS.
C.sub.T --a single input control pin which is connected to the node between timing capacitor 14 and timing resistor 16. The signal at pin C.sub.T controls both outputs H.sub.O and L.sub.O.
R.sub.T --a pin which is connected to the other terminal of timing resistor 16.
V.sub.B --a pin connected to the node of diode 22 and capacitor 24, which acts as a "bootstrap" circuit to provide power for the operation of the high side switch.
H.sub.O --an output pin to the gate (or a resistor 26 to the gate) of the high side MOSFET 40.
V.sub.S a pin to the center tap of the totem-pole or half bridge connected MOSFETs 40 and 42.
L.sub.O --an output pin to the gate (or a resistor 28 to the gate) of the low side MOSFET 42.
COM--a pin connected to the negative or ground terminal.
Resistor 18 and a capacitor 12 provide the IC 30 with its dc and ac power requirements. The resistor 16 and the capacitor 14 control the oscillation frequency according to the equation: ##EQU1##
A diode 22 and a capacitor 24 form the "bootstrap" supply for the floating CMOS driver circuit within the IC. Resistors 26 and 28 dampen LC ringing on the gates of the power MOSFETS 40 and 42 and also serve to buffer the IC 30 from the power stage.
The load circuit, which includes the inductor 46 and the resonant capacitor 52, also includes blocking capacitors 56 and 58, a positive-temperature-coefficient (PTC) resistor 54, and a lamp 50. A capacitor 44 normally controls the dV/dt observed at the Vs node to minimize radiated EMI.
A drawback of this basic circuit is that if the lamp is either broken (such as at the end of its operating life) or is removed from the circuit, catastrophic failure of other components within the circuit may result. Therefore, users of the gate driver IC 30 must typically design additional external circuitry to sense the fault conditions and then turn off the IC. Preferably, both outputs of the gate driver IC turn off under a turn-off condition.
Because the gate driver IC is self-oscillating, one of the gate driver outputs L.sub.O and H.sub.O -V.sub.S is always on, except for the short "deadtime" shown in FIG. 2. Under normal operating conditions, either the MOSFET 40 or the MOSFET 42 is on. As a result, turning off the gate driver IC simply by externally shunting the timing capacitor 14 to ground, as shown in FIG. 3, for example, is not sufficient to protect the circuit.
FIG. 3 shows the circuit of FIG. 1 modified to include a transistor 60 which shunts the input control capacitor 14 to ground when the lamp is removed. A voltage divider formed by resistors 62, 64, 66 and a capacitor 68 form the sensing circuit. Under normal operating conditions, the voltage at node V.sub.A is approximately equal to one-half the dc supply voltage, V.sub.BUS /2, when capacitors 56 and 58 are of identical value. The only difference between the voltage at node V.sub.A and the voltage at the node located at the midpoint between capacitors 56 and 58 results from the voltage drop across the filament of the lamp 50.
Under normal operating conditions, the voltage drop across the filament is relatively small, namely only a few volts, and the voltage at node V.sub.C is insufficient to turn on the shunt transistor 60. If the lamp is removed, however, the voltage at node V.sub.A rises, as does the voltage at node V.sub.C, such that the transistor 60 turns on. The values of the resistors 62, 64, 66 are chosen such that the circuit never turns on the transistor 60 during normal operating conditions but always turns on the transistor 60 when the lamp is removed or fails. The capacitor 68 also forms part of a low pass filter in the turn off response circuit, thereby increasing noise immunity.
The circuit shown in FIG. 3, however, does not shut down both of the power MOSFET devices 40 and 42 when the lamp is removed from the load circuit. Under this no-lamp load condition, the C.sub.T pin of IC 30 would be shunted to ground by the transistor 60, which halts the IC's internal oscillator and its output switching, as desired. However, despite having turned off the output of the half bridge, transistor 42 remains on.
Another approach to shutting down both MOSFETs 40 and 42 under a fault condition is to shunt the V.sub.CC pin of the IC ground, as shown in FIG. 4. Here, the sensing circuit is essentially the same as FIG. 3, but an SCR 70 shunts the V.sub.CC pin through resistor 72 to shut down the output.
A drawback of the circuit of FIG. 4 is that when the fault condition ends, such as when the lamp is replaced in its socket, the entire power-up sequence must be repeated because the supply voltage V.sub.CC that is supplied to the chip has been discharged below its undervoltage threshold. In fact, the circuit relies on the undervoltage lockout circuit of IC 30 to turn both of power transistors 40, 42 off.
Another drawback of the circuit of FIG. 4 is that the SCR 70 is a more expensive component than the NPN transistor 60 of FIG. 3.
Moreover, a resistor 72 must be included into the V.sub.CC capacitor discharge path to slow down the dV/dt at the V.sub.CC pin. The dV/dt must be limited because the supply voltage to the gate driver output stages may turn off before the output stages have fully discharged the gates of the power MOSFETs. For example, if the upper power MOSFET 40 is on and the supply voltage is rapidly brought to 0V, the transistor 40 cannot be turned off and is effectively left with a charge (or voltage) on its gate with only the inherent gate-to-source leakage to discharge the MOSFET. The residual charge can cause catastrophic failure if the IC 30 is restarted when the upper MOSFET 40 is still on. When the IC 30 restarts, namely, when its V.sub.CC voltage exceeds the rising undervoltage lockout threshold, the lower MOSFET 42 turns on first. If transistor 40 is still on when transistor 42 turns on, a short will be present across the dc bus and the ac line that will, at the very least, blow a fuse and more likely cause the failure of either one of or both of the power MOSFETs.